The present invention relates to an improved structure for field effect transistors (FETs). More specifically, an improved FET structure is proposed for high frequency switching applications into inductive loads.
There are many applications that require switching current in inductive loads. For many power and high frequency switching applications, a typical output stage has power MOSFET transistors, usually the NMOS type. For convenience, the power FET of the NMOS type will also be referred to herein as an NFET. Similarly, the power FET of the PMOS type will also be referred to herein as a PFET. FIGS. 1a and 1b show cross sections through generic power NFET transistors with current flowing in the lateral and vertical directions, respectively. Referring to FIG. 1a, the voltage on the gate 107 controls the lateral current flow towards drain contact 106. The body diffusion region 101 contains the N+ source diffusion 103 and the P+ contact diffusion 102. The source N+103 and the body P+ 102 are normally shorted by the source metal, thus allowing the body capacitors to be easily charged and discharged.
Similarly, for the vertical NFET shown in FIG. 1b, the gate 117 controls the lateral current flow which then turns to the vertical direction to be collected by the buried drain 116. Again, the body diffusion 111 contains the N+ source diffusion 113 and the P+ contact diffusion 112. For the same reason mentioned above, the body P+ 112 is shorted to the source N+ 113 through the source metal. It will be understood that above discussion also applies to the PFET transistor with the provision that the diffusion types are interchanged and the voltages and currents are reversed.
FIG. 1c shows another NFET structure which includes a Schottky diode between body and drain. The DMOS part of this structure operates similarly to the devices in FIGS. 1a and 1b, having main body diffusion 121, P+ contact diffusion 122, the N+ source diffusion 123, and the drain diffusion 126. The gate electrode 127 controls the current conduction of the DMOS device. Two additional p-body diffusions 124 shield the vertical Schottky diode formed on top of the epitaxial layer.
FIG. 3 shows the usual schematic symbol used for power FETs. The power NFET 301 is depicted with a body diode 302 between body and drain. Similarly the PFET 303 is shown with the body diode 304 connected to the drain. Using power FETs to switch currents through inductive load allows fast switching time and lower power dissipation. Some common configurations for power stages intended to drive inductive loads are shown in FIGS. 5a and 5b which illustrate an NFET only configuration and a complementary FET configuration, respectively. The low side NFET in either configuration (i.e., NFET 503 or 513) has an internal source-drain diode (504 or 514), which is the actual body/drain junction. On the high side, the power NFET 501 (or PFET 511) has an internal source/drain diode 502 (or 512). The load consists of an inductor 505 (or 515) in series with load impedance 506 (or 516).
During switching, only one power device in each configuration is allowed be conductive, to avoid shoot-through currents. The inductive load forces the output node voltage to go outside the rail voltage, i.e., above the rail 507 (or 517) and below rail 508 (or 518). The voltage swing is clamped by the diodes 502 and 504 (or 512 and 514). As will be understood, a significant drawback of such configurations is due to the large charge storage in the internal body diodes of the power devices which become forward biased when the inductive voltage swing is clamped to the rails. This diode charge storage severely increases the power dissipation as well as aggravates the voltage spikes due to parasitic wire inductance in the circuit.
The usual solution to this charge storage problem is to use external Schottky diodes 509 and 510 (or 519 and 520) between the output node and the rails. Unfortunately, this solution adds significant costs to the power circuit and imposes severe constraints on the board layout as any parasitic inductance can increase the voltage spike on the intrinsic transistor and can turn on its internal diode. Even with the best board layout the series lead inductance of the external Schottky diodes can produce significant charge injection and attendant power losses in the power transistors.
The integration of a Schottky source-drain diode as discussed above with reference to FIG. 1c has been suggested as a solution. In principle, such a solution would reduce most of the charge injection in the epitaxial layer by diverting the forward current through the Schottky source-drain diode. However, this method has two important drawbacks: the Schottky source-drain diode significantly increases the device area, and the Schottky contact has to be of very high quality to sustain the high voltage between the drain and the source.
In view of the foregoing, there is a need for providing efficient, integrated solutions for switching inductive loads which mitigate the effects of the internal body diodes of switching devices.
According to the present invention, switching device structures and switching circuits are provided which avoid the above-described disadvantages. According to specific embodiments, the use of external freewheeling diodes is obviated by the use of the power FETs themselves as clamping devices during inductive spikes. According to such embodiments, a power FET configuration is provided in which the body diode does not turn on when the output potential goes outside the rail voltage range. Rather, the FET itself turns on and the inductor current is directed through the MOSFET channel rather than the bipolar body diode. This saves the cost of external clamping diodes, enables increases in the frequency of operation, and reduces switching power losses.
According to a specific embodiment, an improved power FET structure is provided which prevents the turn-on of the device""s body diode when driving an inductive load. One NFET embodiment has a Schottky type contact between the source metal and the P-body diffusion region, i.e., there is no P+ diffusion in the P-body region. Similarly, a PFET embodiment has a Schottky contact between the source metal and the N-body region, i.e., there is no N+ diffusion in N-body region.
According to more specific embodiments, the improved power FET of the present invention is used to construct a power stage for driving inductive loads. The circuit may use two NMOS devices for high side and low side drive, or may use a complementary stage with a PFET on the high side and an NFET on the low side. When current is flowing through the low side FET and this FET is switched off, the inductive load forces the output voltage above the high rail. During the switching time, the high side is kept turned off, by shorting the gate to source. However, when the output voltage rises above the high rail voltage, the high side FET turns on as a reverse conducting FET, while the body diode is kept off by the reverse bias of the Schottky contact. As will be understood, a similar analysis applies to the situation in which switching current flowing through the high side FET is turned off and the output voltage is inductively forced below the low rail voltage.
According to another embodiment, a power stage implemented using the improved FETs is switched as described above except that the FET which is near the inductively pumped rail is actively turned on by applying a corresponding gate voltage. According to a more specific embodiment, this gate turn-on is delayed from the switching edge such that an even greater reduction in power loss may be achieved while avoiding the risk of shoot through currents.
Thus, the present invention provides a field effect transistor which includes a body diffusion region having a source diffusion region therein. The field effect transistor further includes a metal source contact adjacent the body diffusion region and the source diffusion region. The metal source contact forms a Schottky type contact with the body diffusion region. According to another embodiment, this field effect transistor structure is employed for the high and low side devices in a circuit for driving inductive loads.
According to still another aspect of the invention, a method for driving an inductive load using a low side field effect transistor and a high side field effect transistor is provided. Each of the low side and high side field effect transistors includes a body diffusion region having a source diffusion region therein. Each field effect transistor also includes a metal source contact adjacent the body diffusion region and the source diffusion region which forms a Schottky type contact with the body diffusion region. Where one of the low side and high side field effect transistors is operating in a reverse mode conduction due to an inductive spike, a turn-on voltage is applied to the one of the transistors following a predetermined delay from the other of the transistors being turned off. Application of the turn-on voltage reduces the on-resistance of the one of the transistors.